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Ordering number : EN*4247A
CMOS LSI
LC74730M
On-Screen Display Controller LSI
Preliminary Overview
The LC74730M is a CMOS LSI for on-screen display, a function that displays characters and patterns on a TV screen under microprocessor control. (The LC74730M supports the S-VCR format.) The characters displayed have an 8 x 8 dots structure and a dot interpolation function is provided. The LC74730M display 10 lines of 24 characters each.
Package Dimensions
unit: mm 3073A-MFP30S
[LC74730M]
Features
* Screen format: 10 lines x 24 characters (up to 240 characters) * Character format: 8 (horizontal) x 8 (vertical) (interpolation function provided) * Character sizes: Three horizontal sizes and 3 vertical sizes * Number of characters in font: 64 characters * Display start position -- Horizontal: 64 positions -- Vertical: 64 positions * Blinking: In character units * Types of blinking: Two types with approximately 1.0 sec. and 0.5 sec. * Background color: Four background colors (in internal synchronization mode) (For the PAL-M format: 1 color; blue background) * External control input: 8-bit serial data input format * Built-in sync separator circuit * Built-in synchronization recognition circuit: Recognizes whether or not external synchronizing signals are present * Video output: NTSC and PAL-M format composite outputs, Y-C output
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
D3095HA (OT) No. 4247-1/14
LC74730M Pin Assignment
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg VDD1, VDD2 All input pins CSYNOUT, SYNCJDG, SEPOUT Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIL2 VIN1 VIN2 VIN3 fOSC1 fOSC2 VDD1 VDD2 RST, CS, SIN, SCLK CTRL1 to CTRL3, SEPIN RST, CS, SIN, SCLK CTRL1 to CTRL3, SEPIN CVIN SYNIN The XtalIN oscillator pin (in external clock input mode) Expected value (design target value) The XtalIN and XtalOUT oscillator pins (2fsc) The OSCIN and OSCOUT oscillator pins (LC oscillator) 5 140 7.159 8 12 Conditions min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 2 Vp-p 2 Vp-p 2.5 Vp-p typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 Unit V V V V V V V V mV MHz MHz
Input high-level voltage
Input low-level voltage
Composite video input voltage Input voltage Oscillator frequency
Electrical Characteristics at Ta = -30 to +70C, unless otherwise specified VDD1 = 5 V
Parameter Output off leakage current Input off leakage current Output high-level voltage Output low-level voltage Symbol Ileak1 Ileak2 VOH1 VOL1 IIH IIL Operating current drain IDD1 IDD2 COUT, YOUT, CVOUT CIN, YIN, CVIN CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOH = 1.0 mA CSYNOUT, SYNCJDG, SEPOUT; VDD1 = 4.5 V, IOL = 1.0 mA RST, CS, SIN, SCLK, CTRL1 to CTRL3, SEPIN; VIN = VDD1 CTRL1 to CTRL3, OSCIN: VIN = VSS1 VDD1; all outputs open, crystal: 7.159 MHz, LC: 8 MHz VDD2; VDD2 = 5 V -1 15 20 3.5 1.0 1 Conditions min typ max 10 10 Unit A A V V A A mA mA
Input current
No. 4247-2/14
LC74730M Timing Characteristics at Ta = -30 to +70C, VDD1 = 5 0.5 V
Parameter Minimum input pulse width Symbol tW (SCLK) tW (CS) tSU (CS) tSU (SIN) th (CS) th (SIN) tword twt SCLK CS pin (during the period that CS is high) CS SIN CS SIN The 8-bit data write time The RAM data write time Conditions min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
Data setup time
Data hold time
One word write time
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 Symbol VSS1 XtalIN XtalOUT CTRL1 CSYNOUT OSCIN OSCOUT SYNCJDG Ground Crystal oscillator element connection Crystal oscillator input switching Composite synchronizing signal output LC oscillator External synchronizing signal state judgment output Enable input Clock input Data input Power supply Color signal output Function Ground connection Used to connect the external crystal and capacitors for the crystal oscillator that generates the internal synchronizing signal. Also used for an external clock input. (2fsc: 7.159 MHz) Switches between the external 2fsc clock input mode and the crystal resonator driving mode. Low: crystal oscillator, high: external clock input Outputs the composite synchronizing signal. Outputs the crystal oscillator clock on a reset due to a low level on the RST pin. Does not output any signal on a command reset. Connections for the coil and capacitor that form the oscillator that generates the character output dot clock. Outputs the judgment as to whether or not an external synchronizing signal is present. Outputs a high level when a synchronizing signal is present. Outputs the dot clock (LC oscillator) on a reset due to a low level on the RST pin. Does not output any signal on a command reset. Enable input for serial data input. Serial data input is enabled by a low level. A pull-up resistor is built in. (This input has hysteresis characteristics.) Serial data input clock input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Serial data input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Video signal level adjustment power supply. (Analog system power supply) Color (C) signal output This pin must be level open or connected to ground. Color signal input Chrominance bias output Luminance signal output Color (C) signal input Chrominance signal bias level output Luminance signal (Y) output This pin must be level open or connected to ground. Luminance signal input NTSC/PAL-M switching input Composite video signal output Luminance signal (Y) input Switches the synchronizing signal generator between NTSC and PAL-M formats. Low: NTSC, high: PAL-M Outputs a composite video signal. This pin must be level open or connected to ground. Composite video signal input SEPIN input control Sync separator circuit input Sync separator circuit adjustment Composite synchronizing signal output Vertical synchronizing signal input Reset input Power supply (+5 V) Inputs a composite video signal. Controls whether the VSYNC signal is input to the SEPIN input. Low: VSYNC is input, high: VSYNC is not input. Video signal input to the built-in sync separator circuit. (Input either a horizontal or composite synchronizing signal to this pin if the built-in sync separator circuit is not used.) Adjusts the built-in sync separator circuit. (Connect a capacitor to this pin.) (Leave this pin open if the built-in sync separator circuit is not used.) Outputs the built-in sync separator circuit composite synchronizing signal. (Outputs the SYNIN input signal if the built-in sync separator circuit is not used.) Integrates the SEPOUT output signal and inputs a vertical synchronizing signal. An integration circuit must be connected between this pin and the SEPOUT pin. This pin must be tied to VDD1 if it is not used. The system reset input. A pull-up resistor is built in. (This input has hysteresis characteristics.) Power supply (+5 V: digital system power supply) Description
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
CS SCLK SIN VDD2 COUT NC CIN CBIAS YOUT NC YIN CTRL2 CVOUT NC CVIN CTRL3 SYNIN SEPC SEPOUT SEPIN RST VDD1
28 29 30
No. 4247-3/14
LC74730M Block Diagram
No. 4247-4/14
LC74730M Serial Data Input Timing
Display Control Commands The display control commands have an 8-bit serial input format. Commands consist of a first byte, which includes the command identification code, and data in the second and following bytes. The LC74730M supports the following commands: x COMMAND 0: Display memory (VRAM) write address setup command y COMMAND 1: Display character data write command z COMMAND 2: Vertical display start position and vertical size setup command { COMMAND 3: Horizontal display start position and horizontal size setup command | COMMAND 4: Display control setup command } COMMAND 5: Synchronizing signal control setup command Display Control Command Table
First byte Command Command identification code 7 COMMAND 0 Set write address COMMAND 1 Write character COMMAND 2 Set vertical display start position and vertical character size COMMAND 3 Set horizontal display start position and horizontal character size COMMAND 4 Display control COMMAND 5 Synchronizing signal control 1 1 6 0 0 5 0 0 4 0 1 3 V3 0 2 V2 0 Data 1 V1 0 0 V0 0 7 0 at 6 0 0 5 0 c5 4 H4 c4 Second byte Data 3 H3 c3 2 H2 c2 1 H1 c1 0 H0 c0
1
0
1
0
VS 21 HS 21 TST MOD PH 1
VS 20 HS 20 CB PH 0
VS 11 HS 11 OSC STP BCL
VS 10 HS 10 SYS RST INT
0
0
VP 5 HP 5 NON 0
VP 4 HP 4 EG 0
VP 3 HP 3 BK 1 SN 3
VP 2 HP 2 BK 0 SN 2
VP 1 HP 1 RV SN 1
VP 0 HP 0 DSP ON SN 0
1
0
1
1
0
0
1 1
1 1
0 0
0 1
0 0
0 0
The command identification code in a first byte is retained until the next first byte is written. However, if a display character data write command (COMMAND 1) is written, the LC74730M locks in display character data write mode, and the first byte cannot be overwritten. The command state is reset to the COMMAND 0 state (display memory address setup mode) when the CS pin is set high.
No. 4247-5/14
LC74730M x COMMAND 0 (Display memory write address setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- V3 State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (0 to 9 hexadecimal) Command 0 identification code Set the display memory write address. Function Note
2
V2
1
V1
0
V0
Second byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- H4 State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory character address (0 to 17 hexadecimal) Function Second byte identification bit Note
3
H3
2
H2
1
H1
0
H0
Note: All these registers are set to 0 by a reset due to the RST pin.
y COMMAND 1 (Display character data write setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- -- State 1 0 0 1 0 0 0 0 Command 1 identification code Sets up a display character data write operation Function Note When this command is issued, the LC74730M is locked in display character data write mode until the CS pin goes high.
No. 4247-6/14
LC74730M Second byte
Register content DA0 to DA7 7 6 5 Register name at -- c5 State 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 Character code (00 to 3F hexadecimal) Character attributes off Character attributes on Function Note
4
c4
3
c3
2
c2
1
c1
0
c0
Note: All these registers are set to 0 by a reset due to the RST pin.
z COMMAND 2 (Vertical display start position and vertical size setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- VS21 State 1 0 1 0 0 1 0 1 0 1 0 1 VS11 0 1 VS21 0 1 VS10 VS20 0 1 H per dot 3 H per dot 0 1 H per dot 3 H per dot 1 2 H per dot 1 H per dot 1 2 H per dot 1 H per dot Vertical character size for the first line Vertical character size for the second line Command 2 identification code Sets up the vertical display position and the character size in the vertical direction. Function Note
2
VS20
1
VS11
0
VS10
No. 4247-7/14
LC74730M Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- VP5 (MSB) VP4 State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 The vertical display start position is specified by the 6 bits VP0 to VP5. The weight of the low-order bit is 2 H. If VS is the vertical display start position then: VS = H x (2 2nVPn)
n=0 5
Function Second byte identification bit
Note
4
Where H is horizontal period pulse period.
3
VP3
2
VP2
1
VP1 VP0 (LSB)
0
Note: All these registers are set to 0 by a reset due to the RST pin.
{ COMMAND 3 (Horizontal display start position and horizontal size setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- HS21 State 1 0 1 1 0 1 0 1 0 1 0 1 HS11 0 1 HS21 0 1 HS10 HS20 0 1 Tc per dot 3 Tc per dot 0 1 Tc per dot 3 Tc per dot 1 2 Tc per dot 1 Tc per dot 1 2 Tc per dot 1 Tc per dot Horizontal character size for the first line Command 3 identification code Sets up the horizontal display position and the character size in the horizontal direction. Function Note
Horizontal character size for the second line
2
HS20
1
HS11
0
HS10
Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- HP5 (MSB) HP4 State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 If HS is the horizontal start position then: HS = Tc x (2 2nHPn)
n=0 5
Function Second byte identification bit
Note
4
Where Tc is a single period of the LC oscillator connected the OSCIN and OSCOUT pins. The horizontal display start position is specified by the 6 bits HP0 to HP5. The weight of the low-order bit is 2 Tc.
3
HP3
2
HP2
1
HP1 HP0 (LSB)
0
Note: All these registers are set to 0 by a reset due to the RST pin.
No. 4247-8/14
LC74730M | COMMAND 4 (Display control setup command) First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- TSTMOD State 1 1 0 0 0 1 0 1 0 1 0 1 Resets all registers and turns off display. Normal operating mode Test mode Output the color burst signal. Stop color burst signal output. Does not stop the crystal and LC oscillators. Stops the crystal and LC oscillators. Must be set to 0. Command 4 identification code Sets up the display control state. Function Note
2
CB
Valid only when BCL is high. Valid in external synchronization mode when character display is off. Reset occurs when the CS pin is low, and the reset is cleared when CS goes high.
1
OSCSTP
0
SYSRST
Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- NON State 0 0 0 1 0 1 0 1 0 2 BK0 1 1 RV 0 1 0 1 Blinking on Reverse video character display off Reverse video character display on Character display off Character display on Interlace (262.5 H per field) Non-interlaced (263 H per field) Border off Border on Blinking period: about 0.5 s Blinking period: about 1 s Blinking off Switches the blinking period Blinking during reversed video character display switches the character display between normal display and reversed video display. Switches between interlaced and non-interlaced display Function Second byte identification code Note
4
EG
3
BK1
0
DSPON
Note: All these registers are set to 0 by a reset due to the RST pin.
No. 4247-9/14
LC74730M } COMMAND 5 (Synchronizing signal control setup command) First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- -- State 1 1 0 1 0 3 PH1 1 0 2 PH0 1 1 BCL 0 1 0 1 Background color displayed. No background color (only the background level is set). External synchronization Internal synchronization Valid only in internal synchronization mode Switches between internal and external synchronization. PHASE1 PHASE0 0 0 1 1 0 1 0 1 Background color (phase) /2 3/2 In phase Sets the background color (one of 4 colors). There is only one background color (blue) in PAL-M mode. Command 5 identification code Sets up control of the synchronizing signals Function Note
0
INT
Second byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- SN3 State 0 0 0 0 0 1 0 1 0 1 0 1 SN3 SN2 SN1 SN0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 Number of times HSYNC detected Not detected 16 times 32 times 64 times 128 times External synchronizing signal detection control Function Second byte identification bit Note
2
SN2
1
SN1
0
SN0
Note: All these registers are set to 0 by a reset due to the RST pin.
Display Screen Organization The display screen consists of 10 lines of 24 characters each. Thus the maximum number of characters that can be displayed is 240 characters. However, the maximum number of characters that can be displayed may be fewer than 240 when characters are enlarged. The display memory address consists of a line address (with values from 0 to 9 decimal), and a column (character position) address (with values from 0 to 23 decimal).
No. 4247-10/14
LC74730M Display Screen Organization (Display memory address)
No. 4247-11/14
LC74730M Composite Video Signal Output Levels (internally generated levels)
Output level (IRE) 100 90 46 20 10 8 0 -20 -40 Note: VDD2 = 5.000 VDC
Output voltage (VDC) 3.000 2.857 2.228 1.857 1.714 1.685 1.571 1.285 1.000
No. 4247-12/14
LC74730M Video Signal Output Levels (Y (luminance) signal: internally generated levels)
Output level (IRE) 100 90 28 20 8 0 -40 Note: VDD2 = 5.000 VDC
Output voltage (VDC) 3.000 2.857 1.971 1.857 1.685 1.571 1.000
No. 4247-13/14
LC74730M Video Signal Output Levels (chrominance signal: internally generated levels)
Output level (IRE) 40 20 0 -20 -40 Note: VDD2 = 5.000 VDC
Output voltage (VDC) 3.071 2.786 2.500 2.214 1.928
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4247-14/14

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